There are many instances involving integrated devices where voltage level translator circuits are needed to interface between operations circuits that function at different voltage levels. One operations circuit, for example, may transmit high signals based on a source voltage V.sub.CC. However, a second operations circuit receiving signals from the first might only recognize high signals at a greater voltage V.sub.CC '. Therefore, a translator circuit is electrically interposed between the two operations circuits to receive a signal from the first and, if it is a high signal, to output a signal with an even higher voltage V.sub.CCP that will properly register as a high signal in the second circuit.
One example of a translator in the prior art achieves this result in two distinct charging steps interrupted by a delay. As an input signal changes from low to high, this first prior art translator will begin to charge its output signal to V.sub.CC. A portion of the translator's circuitry, however, does not immediately register the change in the input signal due to a delaying element incorporated into the translator. Once the intermediate step of charging the output to V.sub.CC is complete, the delaying element finally transmits the changed input to the remaining circuitry, which then completes the translation process by charging the output from V.sub.CC to V.sub.CCP.
Such a translator, however, requires several transistors as well as logic devices, resulting in a relatively large circuit, which runs contrary to the desired goal of saving die space. Further, it should be noted that the proper delaying element must be chosen in advance of using the translator in non-test operations. If the delay is not long enough to allow the output signal to initially charge to V.sub.CC, a new delaying device must be chosen to accommodate the translator circuit. Conversely, too long of a delay runs contrary to the desired goal of quick circuit operations. Therefore, it would be desirable to have a translator that is not only smaller but is also capable of translating an input signal at a faster rate without having to pick-and-choose the proper delaying element.
A second translator in the prior art attempts to do just that by directly driving its output to V.sub.CCP, with no transition stage at V.sub.CC. While this second prior art translator is smaller and faster than the first, one of ordinary skill in the art can appreciate that the direct translation to V.sub.CCP requires a larger charge pump than one used in the two stage translator. As a result, the larger charge pump uses more of the available operating current. Given the inefficiency in terms of a charge pump's ability to use operating current, a direct translation to V.sub.CCP is not be desirable in certain applications. Therefore, it would be a major advance in the art to have a translator that is smaller and faster than the first prior art example, yet would allow charging to an intermediate voltage and then to V.sub.CCP in order to avoid the inefficiency of the large charge pump used in the second prior art example.